Dynamic random access memories came to the forefront of technology in the early 1970's with the advent of the 1-T memory cell. In this type of structure, a memory storage capacitor is provided with a switching element associated therewith to allow connection to a Bit Line. A plurality of these memory cells are arranged in an array of rows and columns. The gates of the switching elements associated with each memory cell are arranged in rows and connected to a common Word Line whereas each of the gates in a given column is operable to selectively connect the associated memory cell to a separate Bit Line. Each of the memory cells has the capacity to store one bit of data as either a logic "1" or a logic "0".
When the data stored in a memory cell is accessed, the capacitor is connected to the associated Bit Line which has a predetermined charge level associated therewith. The connection of this memory cell capacitor to the Bit Line causes a change in the charge stored thereon, due to either addition of charge thereto from the memory capacitor or depletion of charge therefrom by the memory capacitor. A sense amp is typically provided for sensing this change in charge to determine whether the bit stored in the memory cell was a logic "1" or a logic "0". However, as the density of a memory array increases, the number of memory cells per Bit Line increases and, due to the size constraints, the size of the memory cell decreases. Therefore, technology has continuously evolved such that the size and the associated capacity of the memory cell has been reduced, and the relative size of the Bit Line has increased. Therefore, the ratio of the Bit Line capacitance to the memory cell capacitance has increased, thus requiring novel techniques to sense very small charge variations in the capacitance change due to access of a memory cell.
One other aspect that exacerbates the sensing operation is that the Bit Line is typically loaded down with a great deal of capacitive overhead. One major contributor to this overhead is the sense amp itself, since it is typically configured of a cross-coupled sense amp wherein the gate of one of the cross-coupled transistors is directly connected to the Bit Line. The only way to reduce this capacitance is to significantly reduce the size of the transistors involved, but this also effects the speed and other operating parameters.